The CMOS (Complementary Metal Oxide Semiconductor) inverter is an element which is commonly used in the circuit. The CMOS inverter receives an input signal and outputs an output signal which has a logic inversion with the input signal.
Please refer to FIG. 1. FIG. 1 is a circuit structure diagram of the CMOS inverter according to prior art. As shown in FIG. 1, the inverter comprises a P-channel Metal Oxide Semiconductors (PMOS) transistor T1 and a N-channel Metal Oxide Semiconductors (NMOS) transistor T2. However, the power source voltage Vdd of high voltage level and the power source voltage Vss of low voltage level which are received are constant and invariant that Vdd and Vss are respectively supposed to be 30V and −6V. As the input signal in of high voltage level is inputted, the NMOS transistor T2 is activated, and the inverter outputs the low voltage level −6V of Vss, and then the voltage Vds between the drain and the source of the PMOS transistor T1 is constantly kept to be the absolute value (36V) of the voltage difference of Vdd and Vss. Until the input signal in is changed to be low voltage level, the PMOS transistor T1 constantly suffers the stress voltage of 36V in this period of time. Similarly, as the input signal in starts from low voltage level, and until it changes to the high voltage level, the NMOS transistor T2 also similarly suffers the high stress voltage. As the voltage difference (i.e. the voltage Vds) of Vdd and Vss is larger, and the core transistor in the CMOS inverter is in the higher stress voltage condition in the long period of time, it easily leads to the aging and damage of the transistor, and thus to reduce the usage lifetime of the inverter.